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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a EVAL-AD1896EB one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 ad1896 7.75:1 to 1:8, 192 khz stereo asrc evaluation board overview the ad1896 is a 24-bit, high-performance, single-chip, second generation asynchronous sample rate converter (asrc). the ad1896 supports sample rates up to 192 khz with 7.75:1 downsampling and 1:8 upsampling ranges while maintaining the highest performance. in normal operation, input serial data (@ input sample rate f s_in ) in 3-wire serial format is sourced to the serial input port pins sclk_i, lrclk_i, and sdata_i. the output serial data (@ output sample rate f s _out) is accessed via the output serial port pins sclk_o, lrclk_o, and sdata_o. the lrclk_i and lrclk_o signals define the input and output sample frequency, respectively. the input and output signals are typically asynchronous with respect to each other and to the master clock, mclk_i. the ad1896 has very flexible serial input and output data ports for glueless interconnection to audio dacs, dsps, digital inter- face receivers (dir), and digital interface transmitters (dit). the ad1896 input and output serial data ports can be config- ured in left-justified, right-justified (16, 18, 20, and 24 bits), i 2 s, or tdm mode. top-level pins are provided for controlling the data formats and other functional modes of the ad1896 without any serial programming. other features include bypass mode, matched phase mode, group delay selection of the digital filter, mute control, and mute flag pin for an internal error flagging. please refer to the ad1896 data sheet for the detailed product description. the overall setup of the evaluation board is described briefly including jumper settings. the ad1896 evaluation board uses a 9 v to 15 v dc source. clean regulated 5 v and 3.3 v are generated to power the ad1896 and other on-board compo- nents. separate 5 v supplies are used for analog and digital sections. op amps used for the analog filtering are powered from 15 v. please refer to appendix a for the block dia gram, schematics, layout plots, bill of materials, and pld code. integrated circuit functions ad1896 asrc (u13) asynchronous sample rate converter cs8414 spdif receiver (u1) receives the digital signal from an external source in spdif/ aes format and recovers the data and clocks. the 3-wire sig- nals are then sourced to the ad1896 input serial port. spdif receiver supports sample rates up to 96 khz. cs8404 spdif transmitter (u6) encodes the ad1896 output (3-wire format) in spdif format. spdif transmitter supports sample rates up to 96 khz. ad1852 stereo dac (u12) stereo dac for converting the ad1896 output into stereo an alog outputs. supports up to 192 khz sample rates unlike spdif transmitter. input cpld (u2) this pld is used to control the input serial port signals of the ad1896. in addition, it controls spdif receiver and other control signals of the ad1896. output cpld (u3) this pld controls the output serial port signals of the ad1896 as well as the spdif transmitter and stereo dac ad1852. in addition to these components, there is a circuit that divides the master clock of the ad1896 by two or three, based on the master/slave clock mode and generates the on-board signals 256 f s , ext256 f s , and 128 f s (figure 9 of the ad1896eb schematic). if the ad1896 output port is operating in 768 f s master mode, then the master clock is divided by three; and if the ad1896 output port is operating in 512 f s master mode, then the master clock is divided by two. the 256 f s clock (for dac) is divided by two to generate the 128 f s master clock for spdif transmitter.
rev. 0 C2C EVAL-AD1896EB the following section highlights key jumpers and switches on the evaluation board. please refer to the ad1896 evaluation board schematic for more details. these switches and jumpers configure the ad1896 and other components, such as, spdif receiver, transmitter, and stereo dac. switch and jumper functions ? s1 is used to switch the mux inside the pld (u2) between the digital interface receiver (dir), the cs8414 (u1), and the direct digital input (ddi hdr3) signals. the selected signal is sourced to the input serial port of the ad1896. dir selection works in conjunction with the switch s2 as described below. ? s2 selects between the rca spdif input (j1) and the toslink optical input (u4). the selected signal is sourced to spdif receiver and recovered sclk_i, lrclk_i, and sdata_i signals drive the input serial port of the ad1896. ? s3 is used to select the different input interface format of the ad1896 input serial data. total of six input serial modes are possible: lj, i 2 s, rj-24, rj-20, rj-18, and rj-16. refer to the digital audio input signals section for the con figura- tion table iv. note that the input logic pld (u2) reads the s3 selection and controls the ad1896 and spdif receiver cs8414 accordingly. ? s4 selects the master/slave mode of the input and output serial ports of the ad1896. refer to table ii for the mode selection settings. in the slave operation, the corresponding sclk and lrclk signals are externally provided by the target system. in the master mode, these two signals are internally generated from the mclk_i signal at 768 f s , 512 f s , or 256 f s rate. in master mode operation, maximum sample rate for master port is limited to 96 khz. ? s5 resets the ad1896 and other components. ? s6 activates the bypass function of the ad1896 where the input serial data is bypassed to the output serial port without any signal processing. ? s7 is used to mute the ad1896 output serial data as well as the ad1852 stereo dac. ? s8 selects between short or long group delay for the ad1896. ? jp1 jumper is used to select output interface format and word width of the ad1896 output serial data. refer to the digital audio output signals section for configuration tables v and vi. again, the output logic pld (u3) decodes the jp1 signals and configures the ad1852 dac and cs8404 spdif transmitter to match the output data format of the ad1896. ? jp2 selects the internal interpolation ratio of the ad1852 stereo dac (u12). based on the sample rate, 8 , 4 , or 2 interpolation could be selected. dac should be configured in 8 , 4 , or 2 mode for 48 khz, 96 khz, or 192 khz sample rates, respectively. ? jp3 enables the automute feature where the ad1896 mute_in will be asserted if the mute_out output from ad1896 is set high. the mute_out is set high when sample rate of lrclk_i and lrclk_o changes. ? jp4 jumper selects between an on-board clock oscillator (12.288 mhz) and on-board third order overtone crystal oscillator (33.8688 mhz) for master clock (mclk_i) of the ad1896. please refer to table ix for the maximum allowable sample rates for 76 f s , 512 f s , and 256 f s master mode with 33.8688 mhz master clock. the on-board clock oscillator (12.288 mhz) is enabled only for the slave mode operation of the ad1896 (switch s4 position 7). ? 10-pin header hdr1(tdm_in) is used to input the tdm_in data from the sharc ? dsp board. ? 10-pin header hdr2 (tdm_out) is used to receive the tdm_out data from the ad1896 to sharc dsp board. ? 10-pin header hdr3 (ddi) is used to drive the input serial port signals sclk_i, lrclk_i, and sdata_i in 3-wire format from an external source. ? 10-pin header hdr5 (ddo) is used to drive the output serial port signals sclk_o, lrclk_o and sdata_o in 3-wire format from an external source. leds ? ds1 (verf) is illuminated when validity+error flag out- put on spdif receiver cs8414 goes high, indicating problems with spdif receiver or missing audio signal to the spdif receiver. ? ds2 (preemp) indicates the pre-emphasized data to the spdif receiver. ? ds3 (3.3 v) is illuminated when 3.3 v dc supply is present to power up the vdd_core of the ad1896. ? ds4 (avdd = 5 v) is illuminated when analog supply to the stereo dac ad1852 is present. ? ds5 (right channel) and ds6 (left channel) dac zero status leds are illuminated when no input signal is present to the stereo dac ad1852 (u12). ? ds7 (audio) is illuminated when the spdif receiver cs8414 is receiving audio data. sharc ? is a registered trademark of analog devices, inc.
rev. 0 C3C EVAL-AD1896EB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 mute_in reset smode_in_2 smode_in_1 smode_in_0 bypass dgnd grpdlys mclk_i mclk_o sdata_i vdd_io lrclk_i sclk_i s6 s5 s7 jp4 crystal osc./external clk ddi-hdr3, spdif-j1, toslink-u4 s3 (8-position switch) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ad1896 mute_out wlngth_out_1 wlngth_out_0 smode_out_1 smode_out_0 tdm_in dgnd mmode_2 mmode_1 mmode_0 sclk_o vdd_core sdata_o lrclk_o s4 (8-position switch) ddo-hdr5, spdif-j2, tdm_out-hdr2 tdm in header hdr1 jp1 (4-position jumper) s8 figure 1. key jumpers and switches on the evaluation board table i. pinout table for 10-pin header connectors pin hdr1 (tdm_in) hdr2 (tdm_out) hdr3 (ddi) hdr5 (ddo) 1 5 v (o) 5 v (o) 5 v (o) 5 v (o) 3 tdm_i (i) sdata_o (o) sdata_i (i) sdata_o (o) 5 sclk_o (i/o) sclk_o (i/o) lrclk_i (i/o) sclk_o (i/o) 7 lrclk_o (i/o) lrclk_o (i/o) sclk_i (i/o) lrclk_o (i/o) 2, 4, 6, 8, 10 gnd gnd gnd gnd digital audio input signals input serial port of the ad1896 can be driven in various ways using this evaluation board. 1. rca phone jack (j1) or toslink (u4) optical connector can be used to input the aes/ebu or spdif signal to the spdif receiver cs8414 (u1). spdif receiver generated sclk_i, lrclk_i, and sdata_i signals drive the input serial port of the ad1896. spdif input is supported only when the ad1896 serial input port is in slave mode (switch s4 position 3 to 7) and supports all input serial data formats except r j -24 bit and r j -20 bit (switch s3 positions 2, 3). the spdif receiver limits input sample rates to 96 khz. 2. alternatively, an external data header (hdr3) can be used to directly source all three signals sclk_i, lrclk_i, and sdata_i from an external source. unlike spdif receiver, table ii. input and output serial port modes mmode_[2:0] s4 switch position 2 1 0 master/slave modes 7 0 0 0 both serial ports are in slave mode 6 001 * output serial port is master with 768 f s_out 5 010 * output serial port is master with 512 f s_out 4 011 * output serial port is master with 256 f s_out 3 1 0 0 matched phase mode 2 101 * input serial port is master with 768 f s_in 1 110 * input serial port is master with 512 f s_in 0 1 1 1 *input serial port is master with 256 f s _in * in master mode operation, maximum sample rate for master port is limited to 96 khz. input sample rate up to 192 khz is possible (input port in slave mode) and set by an external source. all input serial data formats and master/slave clock modes are supported. sclk_i and lrclk_i signals of the input serial port are bidirectional signals. logic levels on pins mmode_ [2:0] control the direction of these signals. when the input serial port is in master mode, these signals are generated by the ad1896; whereas, in the slave mode these signals are provided by an external source. mmode_[2:0] pins are set by the 8-posi tion switch s4. tables ii and iii show the master/ slave clock mode corresponding to each switch position. input data format, such as, i 2 s, lj, or rj is set by the logic levels on smode_in_[2:0] pins as shown in table iv. set the 8-position switch s3 on the evaluation board for the proper input data format.
rev. 0 EVAL-AD1896EB C4C table iii. master/slave mode configuration switch input header (hdr3) output header (hdr5) mclk_i jumper sw4 f s_in f s_out sclk_i lrclk_i sclk_o lrclk_o [mhz] jp4 short 0 132.3 khz set externally output output input input 33.8688 2-3 1 66.15 khz set externally output output input input 33.8688 2-3 2 44.1 khz set externally output output input input 33.8688 2-3 3 not used not used input input input input 33.8688 2-3 4 set externally 132.3 khz input input output output 33.8688 2-3 5 set externally 66.15 khz input input output output 33.8688 2-3 6 set externally 44.1 khz input input output output 33.8688 2-3 7 set externally set externally input input input input 33.8688 2-3 table iv. input interface formats smode_in_[2:0] s3 switch position 2 1 0 input interface format 0 0 0 0 left justified 1 001 i 2 s 2 1 1 1 right justified, 24 bits 3 1 1 0 right justified, 20 bits 4 1 0 1 right justified, 18 bits 5 1 0 0 right justified, 16 bits 6 0 1 0 not used 7 0 1 1 not used digital audio output signals similar to the input serial port, output serial data (sdata_o, sclk_o, and lrclk_o signals) can be accessed in three different ways using this evaluation board. 1. refer to figure 8. direct digital output header (hdr5) or, alternatively, tdm_out header (hdr2) can be used to monitor the output serial data of the ad1896 (sdata_o signal) in the digital form. hdr5 provides lrclk_o, sclk_o, and sdata_o in 3-wire interface format; whereas, hdr2 should be used in tdm mode to interface the tdm output data to the s harc dsp board. 2. spdif output through connector j2, which is generated by the spdif transmitter cs8404. in this case, sclk_o, lrclk_o, and sdata_o from ad1896 are encoded in the spdif signal. similar to the spdif receiver, the output sample rates above 96 khz are not possible due to the transmitter functionality. note that spdif output is sup ported only for the output port in 768 f s_out , 512 f s_out , and 256 f s_out master mode (switch s4 positions 4, 5, 6). 3. rca jack j6 and j7 provide stereo left and right analog output signals from ad1852 dac. refer to figure 10. interpolation ratio of the dac needs to be set based on the sample rate and set by jumper jp2. dac analog output is supported only when the ad1896 output port is configured in 768 f s_out , 512 f s_out , and 256 f s_out master mode (switch s4 positions 4, 5, 6). sclk_o and lrclk_o signals of output serial port are bidirectional signals. logic levels on pins mmode_ [2:0] control the direction of these signals. please refer to table ii for the switch position s4 setting to control the master/slave mode of the output serial port. the output interface mode, such as i 2 s, lj, rj, and tdm mode, is set by the pins smode_out_[2:0]. also, the output port has two more pins wlngth_out_[1:0] to set the output word width to 24, 20, 18, or 16 bits. the logic levels on smode_out_ [1:0] and wlngth_out_ [1:0] pins allow different serial output data formats. as shown in tables v and vi, set the jumpers one and two of jp1 for the word width and three and four of jp1 for the output data format. table v. output interface formats smode_out_[1:0] jp1[4:3] 1 0 interface format 00 0 0 left-justified (lj) 01 0 1 i 2 s 10 1 0 tdm mode 11 1 1 right-justified (rj) table vi. output signal word width wlngth_out_[1:0] jp1[2:1] 1 0 word 00 0 0 24 bits 01 0 1 20 bits 10 1 0 18 bits 11 1 1 16 bits
rev. 0 EVAL-AD1896EB C5C default configuration the default configuration of this evaluation board is highlighted in tables vii and viii. the ad1896 is configured in 24-bit input and output data format, with input serial ports in slave mode and output serial port in (768 f s ) master mode. in this configuration, input serial port needs to be driven by an external system, such as, audio precision, for the slave mode operation. an on-board third overtone crystal oscillator at 33.8688 mhz clocks the ad1896. since the output serial port is configured in 768 f s master mode and the ad1896 is clocked by 33.8688 mhz clock, the output sample rate will be 44.1 khz for this configuration. the maximum input sample rate for this case can be up to 192 khz based on the requirement that the ad1896 master clock must be higher than 138 times the maximum input or output sample rate. the ad1896 can be clocked by secondary on-board clock oscillator (u15) by first inserting the desired clock oscillator in socket u15 and then switching the clock source selection from on-board crystal to clock oscillator (u15) by jumper jp4; however, clock oscillator is enabled for slave mode only (switch s3 position 7). the evalua- tion board contains 12.288 mhz (u15) clock oscillator. the operating and quiescent currents for the 12 v dc supplies are listed below. +12 v quiescent current ~250 ma C12 v quiescent current ~5 ma +12 v normal operation current ~300 maC360 ma C12 v normal operation current ~5 ma sclk lrclk sdata sclk_o lrclk_o sdata_o sclk_i lrclk_i sdata_i sclk lrclk sdata ap1 transmitter ad1896 ap2 receiver figure 2. input and output serial port direction in default configuration table vii. default jumper/switch settings dac input output master/slave interpolation clock group bypass mode mode mode ratio select source delay mode mute (s3) (jp1) (s4) (jp2) (jp4) (s8) (s6) (s7) position 0 position 1, 2, 3, 4 position 6 position 1, 2 position 2, 3 pushed up pushed pushed shorted shorted shorted down down lj-24 bits lj-24 bits output port 48 khz 33.8688 mhz short off off master, sample crystal 768 f s_out rate oscillator table viii. default evaluation board configuration dac input source output source interpolation input output master/slave (hdr3, hdr1, (hdr2, hdr5, ratio select clock source mode (s3) mode (jp1) mode (s4) j1, u4) j2) (jp2) (jp4) lj x lj-24 x both ports in direct x spdif 96/ 48 x on-board x slave mode input 33.8688 mhz crystal i 2 si 2 s-24 o_mas_768 x tdm_in direct x 192/ 48 x external output 256 f s clock rj-24 rj-24 o_mas_512 spdif tdm_out rj-20 rj-20 o_mas_256 toslink rj-18 rj-18 matched group delay bypass mode automute mute phase (s8) (s6) enable (jp3) (s7) rj-16 rj-16 i_mas_768 short x enable enable x enable tdm i_mas_512 long disable x disable disable x i_mas_256
rev. 0 EVAL-AD1896EB C6C default setup sclk lrclk sdata sclk_o lrclk_o sdata_o sclk_i lrclk_i sdata_i sclk lrclk sdata ad1896 u13 mclk_o mclk_i input data: direct digital input header hdr3 (ddi) f s_in set externally f s_out 44.1khz 123 jumper jp4 33.868mhz crystal output data: direct digital output header hdr5 (ddo) ad1852 dac u12 sclk_i lrclk_i sdata_i mclk_i left out right out cs8404 dit u6 spdif output 128 f s 256f s mclk_i sclk_i lrclk_i sdata_i clock divider 256 f s 128 f s figure 3. default setup (refer to figure 5 for detailed setup) table ix. mclk_i frequencies for common sample rates in master mode mclk_i frequency (mhz) sample rate (khz) 256 f s 512 f s 768 f s 44.100 11.289600 22.579200 33.868800 48.000 12.288000 24.576000 96.000 24.576000 external 192 khz clock generator circuit an external circuit can be used to generate the 192 khz clock signals (sclk, lrclk) using on-board 128 f s clock oscilla- tor (u15) running at 24.576 mhz. please refer to figure 4 for the schematic and instructions on how to connect the exter- nal circuit to the ad1896eb. in general, external sclk and lrclk can be used for converting the audio input data to 192 khz rate by connecting sclk to sclk_o (ddo_sclk_o, hdr5 on the ad1896eb) and lrclk to lrclk_o (ddo_lrclk_o, hdr5 on the ad1896eb). on-board spdif transmitter cs8404 (u6) does not support sample rates above 96 khz. attachments appendix a 1. external 192 khz clock generator circuit 2. ad1896 evaluation board block diagram, schematics, and layout plots 3. bill of materials 4. pld code further information ordering information order number is EVAL-AD1896EB for application questions or technical support contact analog devices central applications department at 1-781-937-1428 for assistance. typical performance typical performance of the ad1896 for 44.1 khz:48 khz (asynchronous) sample rate is listed below. 1. dnr, no filter C139 dbfs, 20 hz to 20 khz (C60 dbfs) 2. dnr, a-weighted C142 dbfs, 20 hz to 20 khz (C60 dbfs) 3. thd+n, no filter C120 dbfs, 20 hz to 20 khz (0 dbfs) 4. frequency response 0.015 db, 20 hz to 20 khz (0 dbfs)
rev. 0 EVAL-AD1896EB C7C clr ld ent enp clk rco d0 d1 d2 d3 q0 q1 q2 q3 u2 74ac161 5v mclk 24.576mhz bclk 12.288mhz clr ld ent enp clk rco d0 d1 d2 d3 q0 q1 q2 q3 u3 74ac161 lrclk 192khz j1 5v bclk lrclk mclk header10 ddo direct digital output header notes 1. replace u15, 12.288mhz oscillator with 24.576mhz 2. set s3, i/p if mode to 1 for i 2 s 3. set s4, master/slave mode to 7 4. jumper jp4, mclk_srce pins 1 and 2 5. jumper jp1, o/p i/f mode positions 1, 2, and 4 for 24-bit i 2 s output 6. jumper jp2, select position 1 only for 192khz dac operation 7. set s1 to dir 8. set s2 to select coax or optical input figure 4. 192 khz clock generator for ad1896eb
rev. 0 EVAL-AD1896EB C8C not used (s8) dir cs8414 dit cs8404a oscillator 2 reset direct digital input (hdr3) direct digital output (hdr5) spdif out (j2) spdif in (j1) toslink dac left (j6) dac right (j7) generator 15v input 3v/5v iodv dd reset s5 y1 33mhz output interface mode (jp1) (lj/i2s/tdm/rj) input interface mode (s3) (lj/i 2 s/rj) spdif status mute (s7) (3rd ot) asrc ad1896 3 3 3 3 5v dv dd 3/5 iodv dd 3.3v dv dd 5v dv dd 5v dv dd 5v av dd 3 3 zerol zeror tdm input (hdr1) 3 4 3 2 3 4 3 audio mode pre-emphasis verf input signal source (s1) (dir/ddi) input interface pld mach 4 data data data data data mode i/f mode i/f mode i/f mode i/f mode mute tdm_in tdm output (hdr2) 3 data 2 5v dv dd 5v dv dd 2 3 m/s mode master/slave clock mode (s4) 3 (dit) (dac) (ddio) 256 f s 256 f s 256 f s 256 f s 128 f s 128 f s reset reset reset 256 f s reset output wordlength (jp1) (16/18/20/24 bits) 2 256 f s 512 f s 768 f s bypass (s6) 3 switch s2 regulator 2, 3 prog dvdr dac ad1852 output interface pld mach 4 5v av dd reset 5v dv dd 5v dv dd notes digital data interface signals 1. /2 sclk_0, lrclk_0 2. /3 bclk, lrclk, sdata 3. /4 mclk, bclk, lrclk, sdata figure 5. evaluation board block diagram
rev. 0 EVAL-AD1896EB C9C tdm-i sdata-i sclk-i lrclk-i reset imode0 imode1 imode2 wdlen0 wdlen1 omode0 omode1 cmode0 cmode1 cmode2 sdata-o sclk-o lrclk-o mute 128 f s ext256 f s 256 f s div2/div3 osc-en slvclk0 slvclk1 sample rate converter 96-040c.sch idpm0 idpm1 sdata lrclk bclk mclk deemp mute reset monitor dac 96-050c.sch power supplies and power connections 96-060c.sch tdi-2 tdo-2 tck tms deemp reset ext256 f s tdm-in sclk-o lrclk-o sdata-i sclk-i lrclk-i cmode2 cmode1 cmode0 imode2 imode1 imode0 input interface 96-020c.sch 128 f s tdi-2 tck tms tdo-2 reset lrclk bclk ext256 f s slvclk0 slvclk1 osc-en div2/div3 idpm0 idpm1 cmode2 cmode1 cmode0 sclk-o lrclk-o sdata-o omode0 omode1 wdlen0 wdlen1 sdata output interface 96-030c.sch unless otherwise noted 1.0 all resistor values are expressed in ohms. 1.1 all resistors are 1%, 1/10 w, thick film types. 1.2 all mf resistors are 0.1%, 1/10 w, metal film types. 1.3 r, k, and m are used instead of a decimal point in resistor values. 2. all resistor networks are 5%, 1/16 w types with their values expressed in ohms. 3.0 all capacitor values are expressed in farads. 3.1 u, n, and p are used instead of a decimal point in capacitor values. 3.2 all 100n bypass capacitors are 20%, 50 v, z5u, ceramic monolithic types. 3.3 all non-electrolytic capacitors are 10%, 50 v, x7r, ceramic monolithic types. 3.4 all np0 capacitors are 5%, 50 v, ceramic monolithic types. 3.5 all my capacitors are 5%, 50 v, metallized polyester types. 3.6 all pps capacitors are 5%, 50 v, metallized pps film types. 3.7 all pc capacitors are 5%, 50 v, metallized polycarbonate types. 3.8 all electrolytic capacitors are 20%, 10 v (or higher), aluminum electrolyte types. 3.9 all t a capacitors are 20%, 10 v (or higher), tantalum electrolyte types. 4. for complete information on any component, please see the associated bill of materials. 5. all net names preceded by/are active low signals. figure 6. evaluation board
rev. 0 EVAL-AD1896EB C10C j1 rca spdif input consumer out gnd vcc gnd shield shield torx173 spdif optical input u4 vcc fb3 600z s2 dpdt input select optical / coax rxp rxn c28 68nf m0 m1 m2 m3 u2a m4a5-64/32 cs12/fck sel m0 m1 m2 m3 filt sdata sck fsync c u verf cbl erf mck co /e0 ca/e1 cb/e2 cc/f0 cd/f1 ce/f2 u1a cs8414 s1 dpdt input select spdif / ddi ddi tck tms tdi tdo-2 dir-sdata dir-fsync dir-sck m0 m1 m2 m3 verf audio preemp 12 u5a 74hc04 34 u5b 74hc04 5 6 u5c 74hc04 8 9 u5d 74hc04 r10 392 r38 392 r11 392 ds1 red verf dv dd deemp preemp audio verf ds7 red audio ds2 red preamp cs8414 signal status c s3 octal ad1895 input mode select tst2 c s4 octal master / slave clock ratio select hdr3 direct digital input (ddi) ddi-sdata ddi-lrclk ddi-bclk ddi-sdata ddi-lrclk ddi-bclk r44 100 c67 47pf r41 100 hdr4 isp port dv dd hdr 5 2 hdr1 hdr 4 2 tdm i/o dv dd dv dd hdr 5 2 dv dd dv dd tst1 tdi tck tms tdo clk0/i0 clk1/i1 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 0 4 2 6 0 4 2 6 tdm-i sclk-o lrclk-o ext256 f s tdi-2 tdo-2 tck tms sdata-i sclk-i lrclk-i imode2 imode1 imode0 reset cmode2 cmode1 cmode0 4 2 1 4 2 1 r9 475 c1 10nf c9 100nf c63 47pf c64 47pf c62 47pf r40 100 r39 100 r8 3.4k c1 10nf 1 2 3 4 5 6 r7 75 1 2 3 4 5 6 r1 10k r43 100 c66 47pf r42 100 c65 47pf c10 100nf figure 7. evaluation board
rev. 0 EVAL-AD1896EB C11C dv dd m4a5-64/32 v em1/ c8 rst m0 m1 m2 sdata sck fsync c7/c3 em0/ c9 mck c6/c2 c1 /fc0 pro u c9 / c15 trnpt/fc1 c/sbf cbl/sbc txp txn u6a cs8404 tst9 dv dd tdi-2 tck tms tdo-2 reset 1 5 4 8 2 6 t1 sc937-02 r16 332 r17 90.0 j2 rca spdif out lrclk bclk hdr5 direct digital output (ddo) ext256 f s jp1 hdr 4 2 output mode select wdlngth-0 wdlngth-1 opmode-0 slvclk0 slvclk1 osc-en div2/div3 opmode-1 idpm0 idpm1 sclk-o lrclk-o sdata-o omode0 omode1 wdlen0 wdlen1 cmode2 cmode1 cmode0 1 2 3 4 u8 adm811tart c14 100nf s5 spst reset sdata tdi tck tms tdo clk0/i0 clk1/i1 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 u3a dv dd hdr2 hdr 4x2 tdm output gnd reset mr vcc dv dd 128 f s hdr 5 2 figure 8. evaluation board
rev. 0 EVAL-AD1896EB C12C nc mclk-i mclk-o sdata-i sclk-i lrclk-i bypass imode0 imode1 imode2 mute-i mute-o wdlen1 wdlen0 omode1 omode0 tdm-i sdata-o sclk-0 lrclk-o cmode0 cmode1 cmode2 reset u13a ad1896 tst6 tst7 tst8 sclk-o sdata-o lrclk-o tst3 tst4 tst5 sclk-i sdata-i lrclk-i tdm-i reset imode0 imode1 imode2 wdlen0 wdlen1 omode0 omode1 cmode0 cmode1 cmode2 1y 2y u19a 74hc153 1c0 1c1 1c2 1c3 1g 2c0 2c1 2c2 2c3 2g a b u14a 74ahc02 u14b 74ahc02 u14c 74ahc02 u14d 74ahc02 clk d q q u17a 74ahc74 2 3 4 5 6 1 sd cd u16a 74ahct04 u16b 74ahct04 u16c 74ahct04 74ahct04 u16e 74ahct04 u16f 74ahct04 spdt spdt spdt dv dd bypass r6 10k mute r37 10k jp3 mute enable r36 47.5 jp4 hdr 3 1 mclk source l1 1.8 h y1 r45 22.1 vdd gnd out en u15 osc8 c59 100nf r46 10k mclk mclk/2 mclk/3 dv dd dv dd r5 10k r4 10k 1 2 3 1 2 3 1 2 3 1 2 3 mute s7 bypass s6 not used s8 hdr 2 1 12 1 8 9 10 c56 15pf np0 c55 22pf np0 c57 1nf np0 12 34 33m8688hz clk d q q u18a 74ahc74 2 3 4 5 6 1 sd cd clk d q q u17b 74ahc74 12 11 10 9 8 13 sd cd dv dd 56 5 6 4 13 12 11 div2/div3 dv dd ext256 f s clk d q q u18b 74ahc74 12 11 10 9 8 13 sd cd 256 f s 128 f s 12 11 10 13 spare u16d 98 dv dd dv dd 2 3 mute osc-en 1 8 4 5 slvclk0 slvclk1 %
5 *

rev. 0 EVAL-AD1896EB C13C 5 6 7 u11b op275 r32 549 r25 3.01k c43 1nf np0 j6 rca left output 96/ 48 10 nc 6 192/ 48 7 sdata 27 l/ r clk 25 bclk 26 mclk 2 idpm0 21 idpm1 20 deemp 9 mute 23 clatch 3 cclk 4 cdata 5 zeror 8 zerol 22 pd/rst 24 outl+ 17 outl 16 outr+ 12 outr 13 filtr 14 filtb 19 u12a ad1852 10 11 u5e 74hc04 12 13 u5f 74hc04 c25 100nf c38 15 f ta c26 100nf r15 392 r14 392 ds6 red zero left ds5 red zero right c27 100nf dv dd 1 2 3 4 jp2 hdr 2 2 select idpm0 idpm1 sdata lrclk bclk 256fs deemp mute reset d dd + + c39 15 f ta r21 2.8k r20 2.8k c44 1nf np0 r28 1.5k r29 1.5k r24 3.01k c48 270pf np0 c47 270pf np0 c51 2.2nf pps r34 53.6k 3 2 1 u11a op275 r33 549 r27 3.01k c45 1nf np0 j7 rca right output r23 2.8k r22 2.8k c46 1nf np0 r31 1.5k r30 1.5k r26 3.01k c49 270pf np0 c50 270pf np0 c52 2.2nf pps r35 53.6k r2 10k r3 10k figure 10. evaluation board
rev. 0 EVAL-AD1896EB C14C fb1 600z dvdd c5 100nf 22 7 21 8 va + v d + agnd dgnd fb2 600z c6 100nf cs8414 u1b c7 100nf 16 38 17 39 c8 100nf vcc vcc gnd gnd m4-64/32 u2b gnd gnd 628 dvdd dvdd dvdd c53 100nf 722 821 c54 100nf vdd vcore gnd gnd d3v3 ad1896 u13b c21 100nf 28 18 115 dvdd avdd dgnd agnd fb10 600z c22 100nf ad1852 u12b agnd 11 8 4 c24 100nf v+ v av c c op275 u11c c23 100nf avee dvdd av d d dvdd c29 100nf 16 38 17 39 c30 100nf vcc vcc gnd gnd m4-64/32 u3b gnd gnd 628 14 7 c68 100nf vcc gnd 74hc04 u3b 19 18 c31 100nf vd+ gnd cs8404 u6b dvdd dvdd dvdd dvdd 14 7 c70 100nf vcc gnd 74ahc02 u14e 14 7 c58 100nf vcc gnd 74ahct04 u16g 14 7 c69 100nf vcc gnd 74ahc74 u16c 14 7 c60 100nf vcc gnd 74ahc74 u18c 16 8 c61 100nf vcc gnd 74hc153 u19b dvdd dvdd dvdd dvdd dvdd out out err nr in in sd gnd 8 7 5 4 1 2 6 3 c4 open adp3303-5 u10 c19 100nf c40 100 f c17 100nf + c36 15 f ta fb7 600z fb5 600z av d d ds4 red 5va r13 392 analog ground + cr4 1smb15at3 ta c20 100nf + c42 100 f fb9 600z cr2 dl4001 15vdc j5 avee fb8 600z c18 100nf + c41 100 f av c c dvdd +v out v in adj c13 100nf c32 47 f ta + r18 243 r19 715 4 3 c37 15 f ta + c12 100nf c34 15 f ta + fb4 600z cr3 1smb15at3 15v cr1 dl4001 +15vdc j3 binding post (yellow) gnd j4 binding post (green) binding post (blue) c11 100nf u7 lm317mdt 1 digital ground out out err nr in in sd gnd 8 7 5 4 1 2 6 3 c3 open adp3303-3.3 u9 c16 100nf c35 47 f ta c15 100nf + c33 47 f ta fb6 600z d3v3 ds3 red 3.3v r12 392 + dv dd figure 11. evaluation board
rev. 0 EVAL-AD1896EB C15C figure 12. audio asrc figure 13. component side
rev. 0 EVAL-AD1896EB C16C figure 14. ground planes figure 15. power planes
rev. 0 EVAL-AD1896EB C17C figure 16. bottom layer
rev. 0 EVAL-AD1896EB C18C bill of materials item qty ref detail title mfr p/n mfr name 1 1 lh99321 rev 0 pcb fab ad1895 evaluation lh99321 rev 0 prototype circuits, inc. 2 1 u12 ad1852jrs ic dac stereo 24-bit 192ks/s ssop-28 ad1852jrs analog devices, inc. 3 1 u13 ad1895yrs ic async sample rate converter ssop-28 ad1895yrs analog devices, inc. 4 1 u8 adm811tart ic reset generator sot-143 adm811tart analog devices, inc. 5 1 u9 adp3303ar-3.3 voltage regulator 3 v 3 so-8 adp3303ar-3.3 analog devices, inc. 6 1 u10 adp3303ar-5 voltage regulator 5 v so-8 adp3303ar-5 analog devices, inc. 7 1 u6 cs8404a-cs ic digital audio transmitter 96 khz soic-24l cs8404a-cs crystal semiconductor 8 1 u1 cs8414-cs ic digital audio receiver 96 khz soic-28l cs8414-cs crystal semiconductor 9 1 u7 lm317mdt voltage regulator pos adj dpak lm317mdt motorola 10 2 u2, u3 m4a5-64/32-10vc ic pld cmos isp tqfp44 m4a5-64/32-10vc lattice 11 1 u11 op275gs ic opamp dual bipolar/jfet so-8 op275gs analog devices, inc. 12 1 u14 74ahc02 ic quad 2-input nor so-14 74ahc02d philips 13 2 u17, u18 74ahc74 ic dual d flip-flop so-14 sn74ahc74d texas instruments 14 1 u16 74ahct04 ic hex inverter so-14 sn74ahct04d texas instruments 15 1 u5 74hc14 ic hex schmitt trigger inverter so-14 mm74hc14m fairchild 16 1 u19 74hc153 ic dual 4-input mux so-14 m74hc153m st microelectronics 17 1 t1 sc937-02 transformer signal aes/ebu sc937-02 scientific conversion, inc. 18 1 r45 22r1 ? chip resistor 1% 100 mw thick film 0805 erj-6enf22.1 panasonic 19 1 r36 47r5 ? chip resistor 1% 100 mw thick film 0805 erj-6enf47.5 panasonic 20 1 r7 75r0 ? chip resistor 1% 100 mw thick film 0805 erj-6enf75.0 panasonic 21 1 r17 90r9 ? chip resistor 1% 100 mw thick film 0805 erj-6enf90r9 panasonic 22 6 r39Cr44 100 ? chip resistor 1% 100 mw thick film 0805 erj-6enf1000 panasonic 23 1 r18 243 ? chip resistor 1% 100 mw thick film 0805 erj-6enf2430 panasonic 24 1 r16 332 ? chip resistor 1% 100 mw thick film 0805 erj-6enf3320 panasonic 25 7 r10Cr15, 392 ? chip resistor 1% 100 mw thick film 0805 erj-6enf3920 panasonic r38 26 1 r9 475 ? chip resistor 1% 100 mw thick film 0805 erj-6enf4750 panasonic 27 2 r32, r33 549 ? chip resistor 1% 100 mw thick film 0805 erj-6enf5490 panasonic 28 1 r19 715 ? chip resistor 1% 100 mw thick film 0805 erj-6enf7150 panasonic 29 4 r28Cr31 1.5 k ? chip resistor 1% 100 mw thick film 0805 erj-6enf1501 panasonic 30 4 r20Cr23 2.8 k ? chip resistor 1% 100 mw thick film 0805 erj-6enf2801 panasonic 31 4 r24Cr27 3.01 k ? chip resistor 1% 100 mw thick film 0805 erj-6enf3011 panasonic 32 1 r8 3.4 k ? chip resistor 1% 100 mw thick film 0805 erj-6enf3401 panasonic 33 8 r1Cr6, 10 k ? chip resistor 1% 100 mw thick film 0805 erj-6enf1002 panasonic r37, r46 34 2 r34, r35 53.6 k ? chip resistor 1% 100 mw thick film 0805 erj-6enf5362 panasonic 35 1 c56 15 pf chip capacitor 5% 50 v np0 ceramic 0805 ecu-v1h150jcn panasonic 36 1 c55 22 pf chip capacitor 5% 50 v np0 ceramic 0805 ecu-v1h220jcn panasonic 37 6 c62Cc67 47 pf chip capacitor 5% 50 v np0 ceramic 0805 ecu-v1h470jcg panasonic 38 4 c47Cc50 270 pf chip capacitor 5% 50 v np0 ceramic 0805 ecu-v1h271jcg panasonic 39 5 c43Cc46, 1 nf chip capacitor 5% 50 v np0 ceramic 0805 ecu-v1h102jcx panasonic c57 40 2 c51, c52 2.2 nf chip capacitor 5% 50 v pps film 0805 ech-u1h222jb5 panasonic 41 2 c1, c2 10 nf chip capacitor 10% 50 v x7r ceramic 0805 ecu-v1h103kbg panasonic 42 1 c28 68 nf chip capacitor 10% 50 v x7r ceramic 0805 ecj-2yb1h683k panasonic 43 35 c5Cc27, 100 nf chip capacitor 10% 50 v x7r ceramic 0805 ecj-2yb1h104k panasonic c29Cc31, c53, c54, c58Cc61, c68Cc70 44 5 c34, c36C 15 f chip capacitor 20% 20 v tantalum 7343 ecs-t1dd156r panasonic c39 45 3 c32, c33, 47 f chip capacitor 20% 10 v tantalum 7343 ecs-t1ad476r panasonic c35 46 3 c40Cc42 100 f smd capacitor 20% 25 v aluminum case-f eev-fc1e101p panasonic 47 1 y1 33m8688 hz smd crystal hcm49 hcm49-33.8688 citizen mabjt 48 10 fb1Cfb10 600z chip ferrite bead 600 ? @100 mhz 0805 hz0805e601r steward 49 1 l1 1.8 s chip inductor 20% 0r82 ? rlp167 elj-fa1r8kf panasonic 50 7 ds1Cds7 red chip led 1206led cmd15-21vrd/tr8 chicago miniature lamp, inc. 51 2 cr1, cr2 dl4001 chip diode 50 v 1a sod-87 dl4001 microsemi 52 2 cr3, cr4 1smb15at3 chip transient suppressor 15 v 600 w smb 1smb15at3 on semiconductor 53 2 j1, j2 black insert connector rca female right angle ctp-021 ctp-021-a-s-blk connect-tech products, products, inc. 54 1 j6 white insert connector rca female right angle ctp-021 ctp-021-a-s-wht connect-tech products, products, inc. 55 1 j7 red insert connector rca female right angle ctp-021 ctp-021-a-s-red connect-tech products, products, inc. 56 1 jp3 header 2 1 connector 2p 2 1 male 100ctr sip2 2340-6111tn 3m 57 1 jp2 header 2 2 connector 4p 2 2 male 100ctr hdr2x2 2380-6121tn 3m 58 1 jp4 header 3 1 connector 3p 3 1 male 100ctr hdr3x1 2340-6111tn 3m
rev. 0 EVAL-AD1896EB C19C bill of materials (continued) item qty ref detail title mfr p/n mfr name 59 3 hdr1, header 4 2 connector 8p 4 2 male 100ctr hdr4x2 2380-6121tn 3m hdr2, jp1 60 2 hdr3, header 5 2 connector 10p 5 2 male 100ctr hdr5x2 2380-6121tn 3m hdr5 61 1 hdr4 header 5 2 connector 10p 5 2 male 100ctr shrouded 51138-44624 3m hdr5x2shr 30310-6002hb 62 1 u15 socket 4/8 socket oscillator half size osc8 1108800 aries 63 1 u15 12m288 hz ic cmos oscillator 12.288 mhz osc8 sg-531p-12.288mc epson electronics 64 2 s1, s2 eg-2215 switch slide dpdt side act pcb eg-2215 e-switch 65 2 s3, s4 pt65526 switch rotary 8 pos octal pt65526 apem 66 1 s5 fsm6jsma switch pb no momentary tactile fsm6jsma augat 67 3 s6Cs8 10sp001 switch slide spdt vert act pcb 10sp001 mouser 68 1 u4 torx173 ic fiber optic receiver torx173 toshiba 69 1 j3 yellow connector binding post 111-0107-001 johnson components, inc. 70 1 j4 green connector binding post 111-0104-001 johnson components, inc. 71 1 j5 blue connector binding post 111-0110-001 johnson components, inc. 72 4 spacer snap-in spacer nylon 3/4" snap-in spcs-12 spc technology
rev. 0 EVAL-AD1896EB C20C in_pld.abl module if_logic title 'ad1896 evb input interface logic' //=================================================================================== // file: input_pld.abl // revision date: 03-20-01 // revision by: chirag patel // revision: 1.0 // // description: // // this input interface pld (u2) selects between the external data interface header // (hdr3) and the on-board cs8414 dir (u1) for the ad1896 asrc input signals, depending // upon the spdif/ddi switch position (s1). when the spdif receiver dir is the selected // signal source the digital audio signals, sdata_i, sclk_i and lrclk_i are derived from // the dir output. spdif receiver needs the digital data in the spdif format in order to // generate these signals. when the external data is the selected source the digital // signals from (hdr3) are applied to the ad1896. // signals sclk_i, lrclk_i, ddi_sclk, ddi_lrclk, dir_sclk, dir_fsync on the pld are // bi-directional signals. the direction of these signals are controlled by the // master_slave mode switch position (s4). when the ad1896 input serial port is set in the // master mode, the sclk_i and lrclk_i are generated from the ad1896 input serial port. // on the other hand, these signals are provided from the external source in the slave mode // operation. // pld also decodes the input interface format switch (s3) and sets the interface mode pins // for both the cs8414 dir and the ad1896 asrc. //=================================================================================== library 'mach'; declarations // if_logic device 'm4-64/32-15vc'; "inputs =========================================================================== // tdi, tck, tms pin 4,7,26 istype 'com'; //jtag i/p's dir_sdata pin 1 istype 'com'; //cs8414 dir sdata out spdif_ddi pin 12 istype 'com'; //spdif_ddi switch s1 ddi_sdata pin 22 istype 'com'; //external data input ddi reset pin 23 istype 'com'; //active hi reset output to ad1896 reset_lo pin 44 istype 'com'; //active low reset input ms_mode2, ms_mode1, ms_mode0 pin 24,25,30 istype 'com'; //master/slave mode switch s4 in_mode2,in_mode1,in_mode0 pin 18,15,14 istype 'com'; //input serial mode switch s3 "outputs ========================================================================= // tdo pin 29 istype 'com'; //jtag o/p m0, m1, m2, m3 pin 8,9,10,11 istype 'com'; //spdif_rvr mode select smode_i_0, smode_i_1, smode_i_2 pin 33,32,31 istype 'com'; //input serial mode format for ad1896 sdata_i pin 37 istype 'com'; //serial data input to ad1896 asrc //io signals dir_fsync, dir_sclk pin 2,3; //dir_fysnc and dir_sclk io's ddi_lrclk, ddi_sclk pin 21,20; //external lrclk and sclk io's for hdr3 lrclk_i, sclk_i pin 35,36; //lrclk_i and sclk_i io's to ad1896 asrc "nodes
rev. 0 EVAL-AD1896EB C21C i_sdata, isclk, ilrclk node istype 'com'; //================================================================================ in_pld.abl "macros //input serial data formats // s3 position 0, left-justified lj = ( in_mode2 & in_mode1 & in_mode0); // s3 position 1, i2s i2s = ( in_mode2 & in_mode1 & !in_mode0); // s3 position 2, right-justified 24-bits rj24 = ( in_mode2 & !in_mode1 & in_mode0); // s3 position 3, right-justified 20-bits rj20 = ( in_mode2 & !in_mode1 & !in_mode0); // s3 position 4, right-justified 18-bits rj18 = ( !in_mode2 & in_mode1 & in_mode0); // s3 position 5, right-justified 16-bits rj16 = ( !in_mode2 & in_mode1 & !in_mode0); // s3 positons 6,7 are not used //master_slave mode mapping // s4 position 7, input/output serial ports in slave mode both_slave = (!ms_mode2 & !ms_mode1 & !ms_mode0); // s4 position 6, output serial port in master mode fsx768 o_mas_768 = (!ms_mode2 & !ms_mode1 & ms_mode0); // s4 position 5, output serial port in master mode fsx512 o_mas_512 = (!ms_mode2 & ms_mode1 & !ms_mode0); // s4 position 4, output serial port in master mode fsx256 o_mas_256 = (!ms_mode2 & ms_mode1 & ms_mode0); // s4 position 3, input serial port in matched_phase mode match_phase = (ms_mode2 & !ms_mode1 & !ms_mode0); // s4 position 2, input serial port in master mode fsx768 in_mas_768 = (ms_mode2 & !ms_mode1 & ms_mode0); // s4 position 1, input serial port in master mode fsx512 in_mas_512 = (ms_mode2 & ms_mode1 & !ms_mode0); // s4 position 0, input serial port in master mode fsx256 in_mas_256 = (ms_mode2 & ms_mode1 & ms_mode0); "========================================================================== equations // ad1896 asrc input serial port interface mode select smode_i_2 = rj24 # rj20 # rj18 # rj16; smode_i_1 = rj24 # rj20; smode_i_0 = rj24 # rj18 # i2s; // cs8414 dir interface mode select, dir_fsync and dir_sclk are bi-directional signals. // if ad1896 input serial port is in slave mode, the cs8414 dir rj-24 and rj-20 modes // are not supported. m0 = (rj16 & (both_slave # match_phase # o_mas_768 # o_mas_512 # o_mas_256)) # ((lj # rj24 # rj20 # i2s) & (in_mas_768 # in_mas_512 # in_mas_256)); m1 = ((i2s # rj18) & (both_slave # match_phase # o_mas_768 # o_mas_512 # o_mas_256)) # (i2s & (in_mas_768 # in_mas_512 # in_mas_256)); m2 = rj18 # rj16; m3 = 0;
rev. 0 EVAL-AD1896EB C22C in_pld.abl // io control logic ddi_sclk.oe = (in_mas_768 # in_mas_512 # in_mas_256); ddi_lrclk.oe = (in_mas_768 # in_mas_512 # in_mas_256); dir_fsync.oe = (in_mas_768 # in_mas_512 # in_mas_256); dir_sclk.oe = (in_mas_768 # in_mas_512 # in_mas_256); sclk_i.oe = (both_slave # match_phase # o_mas_768 # o_mas_512 # o_mas_256); lrclk_i.oe = (both_slave # match_phase # o_mas_768 # o_mas_512 # o_mas_256); ddi_sclk = isclk; ddi_lrclk = ilrclk; dir_sclk = ((!isclk) & (lj # rj24 # rj20 # rj18 # rj16)) # (isclk & i2s); dir_fsync = ilrclk; // ad1896 asrc input serial port signals sclk_i = ((lj # rj24 # rj20 # rj18 # rj16 # i2s) & (isclk) & (!spdif_ddi)) # ((((lj # rj24 # rj20) & (!isclk)) # ((i2s # rj18 # rj16) & (isclk))) & (spdif_ddi)); lrclk_i = (spdif_ddi & dir_fsync) # (((i2s & !ddi_lrclk) # (!i2s & ddi_lrclk)) & (!spdif_ddi)); sdata_i = (ddi_sdata & !spdif_ddi) # (((lj#rj24#rj20#rj18#rj16#i2s)&(dir_sdata)) & (spdif_ddi)); // internal node signals isclk = ((ddi_sclk) & (both_slave#match_phase#o_mas_768#o_mas_512#o_mas_256) & (!spdif_ddi)) # ((lj#rj24#rj20) & ((dir_sclk) & (both_slave#match_phase#o_mas_768#o_mas_512#o_mas_256) & (spdif_ddi))) # ((sclk_i) & (in_mas_768 # in_mas_512 # in_mas_256)) # ((i2s # rj18 # rj16) & (dir_sclk) & (both_slave#match_phase#o_mas_768#o_mas_512#o_mas_256) & (spdif_ddi)); ilrclk = ((ddi_lrclk) & (both_slave # match_phase#o_mas_768#o_mas_512#o_mas_256) & (!spdif_ddi)) # ((dir_fsync) & (both_slave # match_phase#o_mas_768#o_mas_512#o_mas_256) & (spdif_ddi)) # ((lrclk_i) & (in_mas_768 # in_mas_512 # in_mas_256)); i_sdata = (ddi_sdata & !spdif_ddi) # (dir_sdata & spdif_ddi); "==================================================================================== end if_logic
rev. 0 EVAL-AD1896EB C23C out_pld.abl //=================================================================================== module if_logic title 'ad1896 evb output interface logic' //=================================================================================== // file: output_pld.abl // revision date: 03-20-01 // revision by: chirag patel // revision: 1.0 // description: // this output interface pld (u3) decodes output interface signals of ad1896 and sources // these signals to the dac, dit and external header (hdr2, hdr5). // signals sclk_o, lrclk_o, ddo_sclk and ddo_lrclk on the pld are bi-directional signals. // the direction of these signals are controlled by the master_slave mode switch position (s4). // when the ad1896 output serial port is set in the master mode, the sclk_o and lrclk_o are // generated from the ad1896 output serial port. on the other hand, these signals are pro- vided // from the external source in the slave mode operation. // // pld also decodes the output interface format and data width jumper header (jp1) and sets // the interface mode pins for the ad1896 asrc, ad1852 dac and cs8404 dit to meet the inter- face // requirements of all three devices in any given mode. //=================================================================================== library 'mach'; declarations // if_logic device 'm4-64/32-15vc'; "inputs =========================================================================== // tdi, tck, tms pin 4, 7, 26 istype 'com'; //jtag i/p's sdata_o pin 3 istype 'com, buffer'; ms_mode2, ms_mode1, ms_mode0 pin 42, 43, 44 istype 'com'; wdlngth1, wdlngth0 pin 19, 18 istype 'com'; opmode1, opmode0 pin 21, 20 istype 'com'; "outputs ======================================================================== // tdo pin 29 istype 'com'; //jtag o/p smode_o_1, smode_o_0 pin 9, 8 istype 'com'; wdlngth_o_1, wdlngth_o_0 pin 11, 10 istype 'com'; osc_en, slvclk1, slvclk0, div2_3 pin 14,12, 13, 15 istype 'com'; idpm1, idpm0 pin 41, 40 istype 'com'; ddo_sdata pin 34 istype 'com, buffer'; sdata_dac_dit pin 22 istype 'com, buffer'; lrclk_dac, sclk_dac pin 36, 35 istype 'com, buffer'; fsync_dit, sclk_dit pin 23, 24 istype 'com, buffer'; m2,m1,m0 pin 31,32,33 istype 'com'; tst9 pin 37 istype 'com, buffer'; //io signals sclk_o, lrclk_o pin 1, 2 istype 'com, buffer'; ddo_sclk, ddo_lrclk pin 30, 25 istype 'com, buffer'; "nodes i_sdata, isclk, ilrclk node istype 'com, buffer'; //================================================================================ out_pld.abl "macros
rev. 0 EVAL-AD1896EB C24C //output serial data formats // jp1[4:3] 0, left-justified lj = (!opmode1 & !opmode0); // jp1[4:3] 1, i2s i2s = (!opmode1 & opmode0); // jp1[4:3] 2, tdm mode tdm = (opmode1 & !opmode0); // jp1[4:3] 3, right-justified rj = (opmode1 & opmode0); // output data bit width settings // jp1[2:1] 0, 24-bits bits_24 = ( !wdlngth1 & !wdlngth0); // jp1[2:1] 0, 20-bits bits_20 = ( !wdlngth1 & wdlngth0); // jp1[2:1] 0, 18-bits bits_18 = ( wdlngth1 & !wdlngth0); // jp1[2:1] 0, 16-bits bits_16 = ( wdlngth1 & wdlngth0); // output serial data format mapping // lj-24 bits lj24 = (lj & bits_24); // i2s-24 bits i2s24 = (i2s & bits_24); // tdm-24 bits tdm24 = (tdm & bits_24); // rj-24 bits rj24 = (rj & bits_24); // rj-20 bits rj20 = (rj & bits_20); // lj-18 bits rj18 = (rj & bits_18); // lj-16 bits rj16 = (rj & bits_16); //master_slave mode mapping // s4 position 7, both serial port in slave mode both_slave = (!ms_mode2 & !ms_mode1 & !ms_mode0); // s4 position 6, output serial port in master mode fsx768 o_mas_768 = (!ms_mode2 & !ms_mode1 & ms_mode0); // s4 position 5, output serial port in master mode fsx512 o_mas_512 = (!ms_mode2 & ms_mode1 & !ms_mode0); // s4 position 4, output serial port in master mode fsx256 o_mas_256 = (!ms_mode2 & ms_mode1 & ms_mode0); // s4 position 3, input serial port in matched_phase mode match_phase = (ms_mode2 & !ms_mode1 & !ms_mode0); // s4 position 2, input serial port in master mode fsx768 in_mas_768 = (ms_mode2 & !ms_mode1 & ms_mode0); // s4 position 1, input serial port in master mode fsx512 in_mas_512 = (ms_mode2 & ms_mode1 & !ms_mode0); // s4 position 0, input serial port in master mode fsx256 in_mas_256 = (ms_mode2 & ms_mode1 & ms_mode0); "==================================================================================== out_pld.abl
rev. 0 EVAL-AD1896EB C25C equations // ad1896 asrc output serial port interface mode and word length select wdlngth_o_1 = wdlngth1; wdlngth_o_0 = wdlngth0; smode_o_1 = opmode1; smode_o_0 = opmode0; // cs8414 dit interface mode select. the chip is configured in the lj mode when ad1896 output format are // set either rj24, rj20, rj18 or rj16. also need to invert the incoming sclk signal in the lj24, rj24, rj20, // rj18 and rj16 mode to match the dit interface requirment for dit_sclk. m0 = lj; m1 = 0; m2 = i2s; // ad1852 stereo dac input serial interface mode select. note that the dac requires serial programing for // rj20, rj18, rj16 mode. since ad1896 evb does not allow serial programming of the ad1852 registers, // ad1852 will be configured in rj24 mode when ad1896 output port is configured in rj20, rj18 and rj16 mode. idpm1 = lj; idpm0 = i2s; // ad1896, dir, dit, ad1852 mclk control logic. based on the master/slave operation of the ad1896 in/out ports, // 33.8688mhz crystal frequency will be divided by either 1, 2 or 3 and the ouput of the di- vider is feed into the dac and dit. // on-board 12.288mhz clock oscillator is enabled only when input and ouput serial ports are configured in slave mode. osc_en = (both_slave); slvclk1 = (o_mas_768) # (both_slave); slvclk0 = (o_mas_512) # (both_slave); div2_3 = (!o_mas_512) & (o_mas_768); // io control logic for bi-directional signals ddo_sclk.oe = (o_mas_768 # o_mas_512 # o_mas_256); ddo_lrclk.oe = (o_mas_768 # o_mas_512 # o_mas_256); sclk_o.oe = (both_slave # match_phase # in_mas_768 # in_mas_512 # in_mas_256); lrclk_o.oe = (both_slave # match_phase # in_mas_768 # in_mas_512 # in_mas_256); // ad1896 asrc output serial port signals ddo_sdata = sdata_o; ddo_sclk = isclk; ddo_lrclk = ilrclk; sclk_o = isclk; lrclk_o = ilrclk; // dac and dit signals sdata_dac_dit = sdata_o; lrclk_dac = ilrclk;
rev. 0 EVAL-AD1896EB C26C sclk_dac = isclk; fsync_dit = ilrclk; sclk_dit = ((!isclk) & (lj # rj24 # rj20 # rj18 # rj16)) # (isclk & i2s); // internal node signals out_pld.abl isclk = ((sclk_o) & (o_mas_768 # o_mas_512 # o_mas_256)) # ((ddo_sclk) & (both_slave # match_phase # in_mas_768 # in_mas_512 # in_mas_256)); ilrclk = ((lrclk_o) & (o_mas_768 # o_mas_512 # o_mas_256)) # ((ddo_lrclk) & (both_slave#match_phase#in_mas_768#in_mas_512#in_mas_256) & (lj # tdm # rj24 # rj20 # rj18 # rj16)) # ((!ddo_lrclk) & (both_slave#match_phase#in_mas_768#in_mas_512#in_mas_256) & (i2s)); "==================================================================================== end if_logic
C27C
C28C c02625C0C12/01(0) printed in u.s.a.

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